A semiconductor circuit or logic device may be designed for any of a wide variety of applications. Typically, the device includes logic circuitry to receive, manipulate and/or store input data, and the same or modified data is subsequently generated at an output terminal of the device. Depending on the type of logic device and/or the circuit environment in which the device is used, the device may include a circuit for providing an internal power signal that is regulated and independent of fluctuations of the externally generated power input signal(s).
A DRAM (dynamic random access memory), formed as an integrated circuit (IC) is an example of such a data storage (or memory) device having an internal power signal circuit. Conventionally, the DRAM receives an external power signal (Vccx) having a voltage intended to maintain a voltage level (or range), for example, of 5 volts measured relative to common (or ground). Internal to the DRAM, a power regulation circuit maintains an internal operating voltage signal (Vccr) at a designated level, for example, of 3.3 volts. Ideally, Vccr linearly tracks Vccx from 0 volts to the internal operating voltage level (3.3 volts in this example), at which point Vccr remains constant as Vccx continues to increase in voltage or fluctuate above this level.
A number of previously-implemented semiconductor power-regulation circuits use a feedback-controlled P-channel transistor at the output of a control circuit, wherein the P-channel transistor is modulated once Vccx reaches the internal operating voltage level (3.3 volts), at which point Vccr remains constant as described above. This approach is disadvantageous, however, because the feed-back-controlled P-channel transistor acts in a manner similar to an operational amplifier whereby a substantial amount of current is consumed during normal operation.
One known approach for mitigating this problem is to implement the control circuit at the input of the P-channel transistor with a low-power standby mode. In this mode, the larger P-channel transistor is deactivated when the IC is not in use, so as to limit the excessive drain of drive current by the feedback-controlled P-channel transistor. Despite this limitation on current consumption, it is still desirable to reduce the overall level of current consumption. This is especially true for IC applications in which the IC is seldom not in use, in which case the beneficial contribution of the standby mode is nominal at best. Moreover, this standby approach introduces a delay to the operation of the IC, for example, during the transition from standby to normal. For fast-responding ICs, such an additional delay is undesirable and often unacceptable.
Accordingly, there is a need for a power regulation circuit which can be used in an IC without experiencing the above-mentioned deficiencies.